9
LTC3700
3700f
The LDO is protected by both current limit and thermal
shutdown circuits. Current limit is set such that the output
voltage will start dropping out when the load current reaches
approximately 200mA. With a short-circuited LDO output,
the device will limit the sourced current to approximately
225mA. The thermal shutdown circuit has a typical trip
point of 150癈 with a typical hysteresis of 5癈. In thermal
shutdown, the LDO pass device is turned off.
Frequency compensation of the LDO is accomplished by
forcing the dominant pole at the output. For stability, a low
ESR ceramic capacitor e2.2礔 is required from LDO to
GND. For improved transient response, particularly at
heavy loads, it is recommended to use the largest value of
capacitor available in the same size considered.
Both the buck and the LDO share the same internally
generated bandgap reference voltage for their feedback
reference. When both input supplies are present, the
internal reference is powered by the buck input supply
(V
IN
). For this reason, line regulation for the LDO output is
specified both with respect to V
IN
and V
IN2
if the buck is
present and with respect only to V
IN2
if the buck is
disabled. The same is true for V
IN2
supply current, which
will be higher when the buck is disabled by the current
draw of the internal reference.
when the buck is operating below 40% duty cycle. How-
ever, once the duty cycle exceeds 40%, slope com-
pensation begins and effectively reduces the peak induc-
tor current. The amount of reduction is given by the curves
in Figure 2.
Soft-Start
An internal default soft-start circuit is employed at power
up and/or when coming out of shutdown. The soft-start
circuit works by internally clamping the voltage at the I
TH
/
RUN pin to the corresponding zero-current level and
gradually raising the clamp voltage such that the minimum
time required for the programmed switch current to reach
its maximum is approximately 0.5msec. After the soft-
start circuit has timed out, it is disabled until the part is put
in shutdown again or the input supply is cycled.
LDO Regulator
The 150mA low dropout (LDO) regulator on the LTC3700
employs an internal P-channel MOSFET pass device be-
tween its input supply (V
IN2
) and the LDO output pin. The
pass FET has an on-resistance of approximately 1.5&
(with V
IN2
= 4.2V) with a strong dependence on input
supply voltage. The dropout voltage is simply the FET on-
resistance multiplied by the load current when in dropout.
OPERATIO
(Refer to Functional Diagram)
DUTY CYCLE (%)
0
10
20
30
40
50
60
70
80
90 100
3700 F02
110
100
90
80
70
60
50
40
30
20
10
I
RIPPLE
= 0.4I
PK
AT 5% DUTY CYCLE
I
RIPPLE
= 0.2I
PK
AT 5% DUTY CYCLE
V
IN
= 4.2V
Figure 2. Maximum Output Current vs Duty Cycle
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